Summary: what is CoPoS?
CoPoS stands for Chip on Panel on Substrate: chips bonded to a panel interposer, which is then bonded to a package substrate. Like CoWoS, it has three layers; the difference is that the interposer changes from a round wafer to a square panel, and reports describe it as a square extension of CoWoS-L / CoWoS-R. According to current public reports, TSMC is targeting 310×310 mm panels, building a pilot line at VisEra in 2026 for equipment and material validation, with trial production in 2027 and volume production at AP7 in Chiayi as early as late 2028.
CoPoS structure: chip, panel, substrate
AI accelerators need the compute chip and several HBM stacks placed very close together to move data at high speed. The solution is an extra "interposer" layer between the chips and the substrate, carrying the dense wiring between chips.
CoWoS has three interposer types: CoWoS-S uses a full silicon interposer, CoWoS-R uses a redistribution layer (RDL) interposer of polymer and copper lines, and CoWoS-L uses an RDL interposer with embedded local silicon bridges (TSMC 3DFabric). Reports describe CoPoS as a square extension of CoWoS-L / CoWoS-R (T Kebang), meaning the interposer is mainly RDL, which is what makes moving it from wafers to panels possible.
Why square panels?
Interposers are square and keep getting bigger. A round wafer's edges can't fit complete squares, and the larger the interposer, the higher the share of wasted edge area. Square panels don't have this problem.
By area alone: a 300 mm wafer is about 70,686 mm² and a 310×310 mm panel is 96,100 mm², about 36% more. But the number of interposers that actually fit differs even more. Here's our estimate for different interposer sizes:
| Interposer size | 300 mm wafer | 310×310 mm panel | Panel / wafer |
|---|---|---|---|
| 50×50 mm | 21 | 36 | About 1.7× |
| 60×60 mm | 12 | 25 | About 2.1× |
| 80×80 mm | 6 | 9 | About 1.5× |
Assumptions: 3 mm wafer edge exclusion, 5 mm panel margin on all four sides, no scribe lines deducted; for comparing orders of magnitude only. Actual numbers depend on TSMC's design rules. Larger interposers usually favor panels more, but in the 80 mm row the panel fits only 3×3, so the ratio is lower; the real benefit depends on how interposer sizes tile.
How does CoPoS differ from CoWoS?
| CoWoS | CoPoS | |
|---|---|---|
| Full name | Chip on Wafer on Substrate | Chip on Panel on Substrate |
| Interposer base | 300 mm round wafer | 310×310 mm square panel |
| Interposer types | Silicon (S), RDL (R), RDL + silicon bridges (L) | Reportedly R/L-type |
| Process equipment | Wafer-level tools (round, 300 mm) | New panel-size tools needed |
| Status | In production, tight | In development (2026 validation) |
| Volume production | In production | Late 2028 to 2029 at the earliest |
| Applications | AI accelerators, HPC | Large AI and HPC chips |
CoPoS isn't meant to replace CoWoS across the board. TSMC has also said panel-level packaging won't replace CoWoS for the largest AI processors in the near term (Tom's Hardware). The more likely outcome is that both coexist, with CoPoS used to expand capacity and lower costs.
CoPoS process flow
TSMC hasn't disclosed the full flow. Based on public information, CoPoS is similar to CoWoS, except the first half is done on panels instead of wafers:
Panel interposer
A release layer is coated on a 310×310 mm carrier, and multiple RDL layers are built; CoWoS-L style also embeds local silicon bridges, ending with micro-bump pads.
Chips onto panel (CoP)
Compute chips and HBM are fluxed and bonded to the panel. After reflow, panel-level deflux cleans flux out of the micro-bump gaps, followed by drying, plasma cleaning, and underfill.
Panel mold & backside
The whole panel is molded and ground, the carrier is removed, and C4 bumps are formed.
Panel dicing
The panel is cut into individual "chip + interposer" modules and cleaned after dicing.
Onto substrate (oS)
Same as CoWoS: flip-chip to substrate, deflux, underfill, lid, ball mount, deflux, test, ship.
For the complete list of steps and a comparison of CoPoS with CoWoS, FCBGA, and the other 8 packages, see Semiconductor packaging flowcharts: CoPoS.
CoPoS timeline
Pilot at VisEra, volume in Chiayi
Plans call for the first pilot line at VisEra in 2026, with volume production at AP7 in Chiayi Science Park.
Source: T Kebang, 2025-06-18Validation year
TrendForce says TSMC is targeting a 310×310 mm substrate size, making 2026 a critical validation period for equipment and material suppliers.
Source: EDN, 2026-06-17Longtan pilot, two tracks
Reports say the pilot line has two tracks: one using solutions from major international equipment makers, the other from Taiwanese equipment makers.
Source: AI Weekly citing The Information, 2026-07-30Trial production
Per TrendForce estimates.
Source: EDNVolume production
TrendForce estimates volume production in the second half of 2028; other reports put it at AP7 in Chiayi from late 2028 to 2029.
Sources: EDN, T KebangNext: glass substrates
After CoPoS, the roadmap turns to glass core substrates, with volume production reasonably estimated after 2030.
Source: TechNews, 2026-06-17
Timelines are from media reports and research firm estimates, not official TSMC announcements.
Wafer to panel: the hurdles
Warpage
Mismatched CTE makes panels warp when heated, hurting alignment and yield — worse with size (TechNews).
Large-area RDL
Fine, uniform RDL across 310 mm is harder than on a wafer.
Handling
Tools built for round wafers need new handling, clamping and alignment.
Wet process
Panel deflux must spray and dry evenly across 310 mm without marks. Panels suit conveyors, but uniformity is the test.
That's why 2026 is seen as the critical period for equipment validation: which tools pass panel-level qualification will shape the supply chain that follows. Reports say more than ten Taiwanese equipment, substrate, and OSAT companies stand to benefit most directly from TSMC's advanced packaging expansion and the CoPoS push (Statementdog, 2026-06-08).
How does CoPoS relate to FOPLP and glass substrates?
| Technology | What it is | Relation to CoPoS |
|---|---|---|
| FOPLP | Panel fan-out: mold and RDL on a panel, usually no interposer | Shared panel know-how |
| CoPoS | Panel 2.5D: panel interposer + substrate | This article |
| Glass substrates | Glass core substrate, with through-glass vias | The next step after CoPoS, estimated after 2030 |
FAQ
What does CoPoS mean?
CoPoS stands for Chip on Panel on Substrate, a panel-level advanced package in development at TSMC. Chips are bonded to an interposer made on a square panel, which is then bonded to a package substrate; it's part of semiconductor back-end processing.
How does CoPoS differ from CoWoS?
Both have the same three layers, chip, interposer, and substrate; the difference is the interposer. CoWoS uses a 300 mm round wafer, while CoPoS uses a 310×310 mm square panel. Square panels waste less edge area, so each one yields more interposers.
When and where will CoPoS be in volume production?
According to current reports, a pilot line is being built at VisEra in 2026 to validate equipment and materials, with trial production in 2027 and volume production at AP7 in Chiayi Science Park from late 2028 to 2029 at the earliest. These are media and research firm estimates, not official TSMC announcements.
How large is the CoPoS panel?
According to TrendForce, TSMC is targeting 310×310 mm in the near term. That's about 96,100 mm², roughly 36% more than a 300 mm wafer, and square, with little edge waste.
Will CoPoS replace CoWoS?
Not in the near term. TSMC has said panel-level packaging won't replace CoWoS for the largest AI processors in the near term; more likely, the two will coexist, with CoPoS expanding capacity.
Is CoPoS the same as FOPLP?
No. Both use square panels, but FOPLP is fan-out packaging, usually without a separate interposer; CoPoS uses a panel-made interposer bonded to a package substrate, making it 2.5D packaging.