Semiconductor Back-End Process Flowcharts: 8 IC Packaging Processes Compared (QFN, BGA, FCBGA, CoWoS)

Q: Is a packaging plant one continuous line?

No. Wafers, substrates, memory, and other materials come from different factories, are prepared separately, and only merge at the bonding step. Each stage uses different carriers (wafers, substrate strips, single units) at different speeds, and there are batch processes such as baking and testing. So an OSAT is a series of standalone tools, with material moved in lots; only short, fixed sequences such as "flux → bond → reflow → deflux" are linked by conveyor.

Q: What is the semiconductor packaging process flow?

There are roughly four stages: wafer preparation (intake, probe, grinding, dicing), assembly (wire bond, flip chip, or wafer-level RDL), protection and contacts (molding, underfill, lid, plating, or ball mount), and test and shipping. Packages differ most in the assembly stage, with step counts ranging from thirty-something to seventy-something.

Q: What's the difference between QFN and BGA?

Both can be wire-bond packages. QFN uses a leadframe with metal pads around the bottom edge as contacts, molded as a strip and then singulated; BGA uses a substrate with a full array of solder balls on the bottom, giving many more contacts. BGA needs ball mounting, so it has an extra deflux step; QFN doesn't.

Q: What's the difference between FCBGA and wire-bond BGA?

In wire-bond BGA, the die faces up and connects to the substrate with metal wires. In FCBGA, the die is flipped and soldered directly to the substrate with bumps, then underfilled. Flip chip gives shorter connections, more contacts, and better heat dissipation, so it's used for high-performance chips like CPUs and GPUs, but it adds bumping, post-flip-chip deflux, and underfill.

Q: What's the difference between CoWoS and InFO?

Both are TSMC advanced packages. InFO is fan-out: dies are placed on a carrier, molded, and RDL is built directly on them with no separate substrate; it's mostly used for phone processors. CoWoS is 2.5D: multiple chips connect to an interposer and then to a substrate; it's used for AI accelerators, with a longer process and more deflux steps.

Q: Why does WLCSP have no substrate?

WLCSP builds the RDL and solder balls directly on the whole wafer, so each diced unit is die-sized and its solder balls go straight onto the circuit board. No leadframe or substrate is needed, which suits small chips in phones.

Q: What packages do 3 nm and 5 nm chips use?

It depends on the product. AI accelerators mostly use 2.5D advanced packaging like CoWoS, CPUs and GPUs use FCBGA, and phone processors use fan-out InFO or flip-chip FCCSP. Advanced-node chips have many contacts and run hot, so wire-bond packaging is rarely used.

Q: What packages do mature-node (28 nm and above) chips use?

Mostly wire-bond packages such as QFN, QFP, and wire-bond BGA, or very small WLCSP. Power management, analog, MCU, and sensor products have few contacts and are cost-sensitive, so wire bonding is the best value.

Q: Which packaging steps require cleaning?

Every package has post-dicing cleaning. Bonding that uses flux (flip chip, ball mount) needs deflux afterward; molding may need deflash; plasma cleaning is common before wire bonding and underfill. For the number of cleaning stations per package, see the comparison table in this article.

Summary: what are the steps in packaging?

Whatever the package, the flow follows roughly four stages: wafer preparation (intake, probe, grinding, dicing) → assembly (connecting dies to a leadframe, substrate, interposer, or RDL) → protection and contacts (molding, underfill, lid, plating, or ball mount) → test and shipping. The difference lies in how the die is connected: wire-bond packages use metal wires, flip-chip packages flip the die and solder it with bumps, wafer-level packages are built on the whole wafer, and 2.5D packages (CoWoS, CoPoS) add an interposer and bond twice. Step counts range from 39 for QFP to 73 for CoWoS.

What packaging does

The front-end fab builds circuits on the wafer, but the dies themselves are fragile and their contacts tiny, so they can't be soldered directly to a circuit board. Packaging does four things:

Protection

Mold and lids shield the die from moisture, dust and stress.

Connection

Tiny die pads become leads or balls a board can take.

Heat dissipation

Leadframes, substrates and lids carry heat away.

Test

Tested before and after, so every unit shipped is good.

All of this is done at OSATs (or a fab's advanced packaging plant), which is why it's called back-end processing. For a full comparison of front end and back end, see How front-end and back-end processing differ.

4 families by connection

Package categories
Category	Connection	Covered here
Wire bond	Face-up die, wired to frame or substrate	QFP / SOP, QFN / DFN, wire-bond BGA
Flip chip	Flipped die, bumps to substrate, underfilled	FCBGA / FCCSP
Wafer level	No substrate; RDL and balls on the wafer	WLCSP, fan-out (InFO)
2.5D	Chips on an interposer, then a substrate	CoWoS, CoPoS

The 8 packages compared

Click a package name to switch to its flowchart
Package	Connection	Carrier	Deflux steps	Other cleaning	Uses
QFP / SOP	Wire bond	Leadframe	0	Grind/dice clean, deflash, plating rinse; plasma (by product)	Power ICs, MCUs, auto
QFN / DFN	Wire bond	Leadframe (strip)	0	Grind/dice clean ×2, deflash; plasma (by product)	Analog, RF, power
Wire-bond BGA	Wire bond	Substrate	1	Grind/dice clean ×2; plasma (by product)	Memory, consumer chips
FCBGA / FCCSP	Flip chip	Substrate	2–3	Bump, strip, reflow, grind, depanel, dice cleans; descum and plasma (by product)	CPUs, GPUs, networking
WLCSP	Bumps to board	Wafer	1 (wafer level)	Pre/post RDL plating, post-strip, post-grind, post-dicing clean; passivation descum ×2, pre-UBM plasma	Small phone chips
Fan-out (InFO)	RDL	Wafer-shaped carrier	1 (wafer level)	Cu post, grind, mold grind, RDL, debond, dice cleans; descum	Phone APs, PMICs
CoWoS	Flip chip ×2	Interposer + substrate	3 (CoW · oS · ball mount)	CMP, RDL, micro-bump, grind, debond, dice cleans; descum and plasma	AI accelerators, HPC
CoPoS	Flip chip ×2	Panel + substrate	3 (CoP · oS · ball mount)	RDL, micro-bump, grind, debond, dice cleans; descum and plasma	AI accelerators (after 2028)

Which package for which node?

The bottom line: packaging is chosen by product needs, not dictated by the node. It depends on contact count, performance, heat, size, and cost. But there's a clear correlation: advanced nodes (7 nm and below) mostly make high-performance chips with many contacts and high heat, which need flip-chip or advanced packaging; mature nodes (28 nm and above) mostly make power, analog, and MCU chips, where wire-bond packaging is enough and cheapest.

Typical wafer process nodes by package
Package	Typical nodes	Typical products
QFP / SOP	Mature 90 nm and above	Auto MCUs, power, industrial
QFN / DFN	Mature 28 nm and above	Power, analog, RF, Bluetooth
Wire-bond BGA	Mature 28 nm and above	Consumer SoCs, networking
FCBGA	40 nm to 3 nm	CPUs, GPUs, switches
WLCSP	Mostly mature 28 nm and above	Small power, sensor, RF dies
Fan-out	Advanced 16 nm and below	Phone processors (the first volume product was Apple's 16 nm A10)
CoWoS	Mainly 7 nm and below	AI accelerators: NVIDIA H100 (4 nm class), B200, B300 (4NP); first volume production was a 28 nm FPGA in 2013
CoPoS	≤3 nm expected	Large AI / HPC chips (after 2028)

General patterns only; the same node may use different packages. For example, among 3 nm phone processors, Apple uses fan-out InFO while most Android phone chips use flip-chip FCCSP. Sources: CoWoS first volume production, TSMC press release; A10 on 16 nm with InFO, Semiconductor Digest; B200 on 4NP with CoWoS-L, TechInsights.

Full flows for 8 packages

Actual flows depend on product design and each plant's process; TSMC hasn't fully disclosed CoWoS and CoPoS details, so these are compiled from public literature and reports.

Leadframe packages (QFP / SOP)

The classic package: die on a metal leadframe, wire bonded, leads on two or four sides. No solder balls, so no deflux.

39 process steps

Nodes: 90 nm+ | auto MCUs, power ICs, industrial

NewsCar engine and body electronics rely on QFP MCUs — the mature chips missing in the 2021 shortage.

QFP / SOP39 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Blue ↗: related DEYly productTeal ↗: related articleHalf blue, half teal ↗: both product and articleDashed box: depends on productBlue box: inline segment linked by conveyorBlue arrow: continues to next stepGreen box: end of flow

Materials: 2 lines in parallel, merging at assembly

Wafer lineFrom the fab

Wafer intakeSteps 1–3
1. 1Wafer intakeShipped from the fab
2. 2Incoming inspectionIncoming QC
3. 3Wafer probeCP, at the fab or OSAT
Grind & diceSteps 4–10
1. 4Apply protective tapeBG tape
2. Grinder cleans inline
  1. 5BackgrindingBack grinding
  2. 6Post-grind cleanRemoves debris
3. 7Detape · tape mountWafer mount
4. Saw cleans inline
  1. 8Wafer dicingWafer saw
  2. 9Post-dice cleanDI spray + spin dry
5. 10Post-dicing inspectionAOI
Wafer to lineSteps 11–13
1. 11Load frame cassetteFrame cassette
2. 12N₂ cabinetBy product
3. 13To assemblyCart, AGV, or OHT

Leadframe lineFrom the supplier

Leadframe intakeStep 14
1. 14Leadframe intakeLeadframe
Leadframe to lineSteps 15–16
1. 15Load magazineMagazine
2. 16To assembly

Die and leadframe merge

Main flow

Assembly
- Attach & bondSteps 17–23
  1. 17Kitting · lot matchingMatch lots, count
  2. 18Plasma before attachBetter adhesion
  3. 19Die attachEpoxy or DAF
  4. 20Epoxy cureCure
  5. 21Plasma before bondCleans pads
  6. 22Wire bondingWire bond
  7. 23Post-bond inspection3rd optical
Mold & form
- MoldingSteps 24–26
  1. 24MoldingMolding
  2. 25Post-mold curePMC
  3. 26DeflashChemical + water jet
- Plating and formingSteps 27–31
  1. Plating: continuous tanks
    1. 27Pre-plating treatmentDegrease · pickle · rinse
    2. 28Lead platingTin plating
    3. 29Rinse & dry
  2. 30Laser markingMarking
  3. 31Trim and formTrim & form
Test and shipping
- TestSteps 32–34
  1. 32Final testFT
  2. 33Burn-in testHigh-reliability
  3. 34Visual inspectionVisual / AOI
- Packing and shippingSteps 35–39
  1. 35Trays or reelsQFP trays; SOP tubes/reels
  2. 36MSL bakeBy MSL
  3. One inline packer does it all
    1. 37Vacuum dry packBag + desiccant + HIC
    2. 38Label · inner box
  4. 39Carton · pallet
  5. ✓ Shipped

QFN / DFN (no-lead leadframe)

Leads hidden underneath; the whole strip is molded, then cut (MAP). Wire bonded, no deflux; cleaning is dicing and deflash.

40 process steps

Typical nodes: mature 28 nm and above | power management, analog, RF, Bluetooth chips

NewsPower, charging and wireless chips in phones, earbuds and watches: small, cool, cheap.

QFN / DFN40 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Materials: 2 lines in parallel, merging at assembly

Wafer lineFrom the fab

Wafer intakeSteps 1–3
1. 1Wafer intakeShipped from the fab
2. 2Incoming inspectionIncoming QC
3. 3Wafer probeCP, at the fab or OSAT
Grind & diceSteps 4–10
1. 4Apply protective tapeBG tape
2. Grinder cleans inline
  1. 5BackgrindingBack grinding
  2. 6Post-grind cleanRemoves debris
3. 7Detape · tape mountWafer mount
4. Saw cleans inline
  1. 8Wafer dicingWafer saw
  2. 9Post-dice cleanDI spray + spin dry
5. 10Post-dicing inspectionAOI
Wafer to lineSteps 11–13
1. 11Load frame cassetteFrame cassette
2. 12N₂ cabinetBy product
3. 13To assemblyCart, AGV, or OHT

Leadframe lineFrom the supplier

Leadframe intakeStep 14
1. 14Leadframe intakeLeadframe
Leadframe to lineSteps 15–16
1. 15Load magazineMagazine
2. 16To assembly

Die and leadframe merge

Main flow

Assembly
- Attach & bondSteps 17–24
  1. 17Kitting · lot matchingMatch lots, count
  2. 18Plasma before attachBetter adhesion
  3. 19Die attachDie attach
  4. 20Epoxy cureCure
  5. 21Plasma before bond
  6. 22Wire bondingWire bond
  7. 23Post-bond inspection
  8. 24Pre-mold plasma cleanBetter mold adhesion
Mold & singulate
- MoldingSteps 25–27
  1. 25Strip moldingMAP molding
  2. 26Post-mold curePMC
  3. 27DeflashWater jet
- Plating and markingSteps 28–30
  1. 28Lead platingSkip with PPF
  2. 29Laser markingMarking
  3. 30Apply dicing tape
- SingulationSteps 31–32
  1. Saw cleans inline
    1. 31SingulationPackage saw
    2. 32Post-dice cleanDust removal + air dry
Test and shipping
- TestSteps 33–35
  1. 33Final testFT
  2. 34Burn-in testHigh-reliability
  3. 35Visual inspectionVisual / AOI
- Packing and shippingSteps 36–40
  1. 36Tape and reelTape & reel
  2. 37MSL bakeBy MSL
  3. One inline packer does it all
    1. 38Vacuum dry packBag + desiccant + HIC
    2. 39Label · inner box
  4. 40Carton · pallet
  5. ✓ Shipped

Wire-bond BGA (PBGA)

Die face-up on a substrate, wire bonded, solder balls below. Balls need flux, so one deflux.

42 process steps

Nodes: 28 nm+ | consumer SoCs, networking, industrial

NewsDRAM and NAND often stack dies, wire bond them and package as BGA.

Wire-bond BGA42 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Materials: 2 lines in parallel, merging at assembly

Wafer lineFrom the fab

Wafer intakeSteps 1–3
1. 1Wafer intakeShipped from the fab
2. 2Incoming inspectionIncoming QC
3. 3Wafer probeCP, at the fab or OSAT
Grind & diceSteps 4–10
1. 4Apply protective tapeBG tape
2. Grinder cleans inline
  1. 5BackgrindingBack grinding
  2. 6Post-grind cleanRemoves debris
3. 7Detape · tape mountWafer mount
4. Saw cleans inline
  1. 8Wafer dicingWafer saw
  2. 9Post-dice cleanDI spray + spin dry
5. 10Post-dicing inspectionAOI
Wafer to lineSteps 11–13
1. 11Load frame cassetteFrame cassette
2. 12N₂ cabinetBy product
3. 13To assemblyCart, AGV, or OHT

Substrate lineFrom the supplier

Substrate intakeStep 14
1. 14Substrate in · bakeRemoves moisture
Substrate to lineSteps 15–17
1. 15Load magazineMagazine
2. 16Dry cabinet storageBy product
3. 17To assembly

Die meets substrate

Main flow

Assembly
- Attach & bondSteps 18–24
  1. 18Kitting · lot matchingMatch lots, count
  2. 19Plasma before attachBetter adhesion
  3. 20Die attachDie attach
  4. 21Epoxy cureCure
  5. 22Plasma before bond
  6. 23Wire bondingWire bond
  7. 24Pre-mold plasma clean
Mold & ball mount
- MoldingSteps 25–27
  1. 25MoldingMolding
  2. 26Post-mold curePMC
  3. 27Laser markingMarking
- Ball mountSteps 28–32
  1. 28Plasma before ballsBy product
  2. Inline ball mount
    1. 29Flux applicationFlux
    2. 30Ball mountBall mount
    3. 31ReflowReflow
    4. 32Post-ball-mount defluxFlux around balls
- SingulationSteps 33–34
  1. Cleaned right after dicing
    1. 33SingulationSingulation
    2. 34Post-dice clean
Test and shipping
- TestSteps 35–37
  1. 35Final testFT
  2. 36Burn-in testHigh-reliability
  3. 37Visual inspectionVisual / AOI
- Packing and shippingSteps 38–42
  1. 38Into traysJEDEC tray
  2. 39MSL bakeBy MSL
  3. One inline packer does it all
    1. 40Vacuum dry packBag + desiccant + HIC
    2. 41Label · inner box
  4. 42Carton · pallet
  5. ✓ Shipped

Flip-chip BGA (FCBGA / FCCSP)

Die flipped and bumped onto the substrate, then underfilled. Same data as the deflux article. FCCSP is the small version, often with molded underfill.

55 process steps

Typical nodes: 40 nm to 3 nm | CPUs, GPUs, network switch chips; high-end products mostly 7 nm and below

NewsCPUs, GPUs and switch chips are all flip chip — too many pins and too much power for wires.

FCBGA55 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Materials: 2 lines in parallel, merging at assembly

Wafer lineFrom the fab

Wafer intakeSteps 1–2
1. 1Wafer intakeShipped from the fab
2. 2Incoming inspectionIncoming QC
BumpingSteps 3–8
1. 3Pre-bump plasma descumDescum
2. 4Bump formationPI · UBM · plate · reflow
3. 5Bump plating cleansPre-treat + rinse
4. 6Post-strip cleanAfter strip & etch
5. 7Post-bump-reflow cleanWafer-level tools
6. 8Wafer probeCP
Grind & diceSteps 9–15
1. 9Apply protective tapeBG tape
2. Grinder cleans inline
  1. 10BackgrindingBack grinding
  2. 11Post-grind cleanRemoves debris
3. 12Detape · tape mountWafer mount
4. Saw cleans inline
  1. 13Wafer dicingWafer saw
  2. 14Post-dice cleanDI spray + spin dry
5. 15Post-dicing inspectionAOI
Wafer to lineSteps 16–18
1. 16Load frame cassetteFrame cassette
2. 17N₂ cabinetBy product
3. 18To assemblyCart, AGV, or OHT

Substrate lineFrom the supplier

Substrate intakeStep 19
1. 19Substrate in · bake
Panel depanelingSteps 20–21
1. Cleaned right after depaneling
  1. 20Panel depanelingRouter, quarter panels
  2. 21Post-depaneling cleanDust removal
Component mountingSteps 22–23
1. Inline SMT
  1. 22SMT passivesFlux · reflow
  2. 23Pad defluxRemoves flux from pads
Substrate to lineSteps 24–26
1. 24Load magazineMagazine
2. 25Dry cabinet storageBy product
3. 26To assembly

Die meets substrate

Main flow

Flip-chip assembly
- BondingSteps 27–31
  1. 27Kitting · lot matchingMatch lots, count
  2. Inline flip chip: conveyor to cleaner
    1. 28Flux dip / sprayFlux
    2. 29Flip-chip attachFlip chip attach
    3. 30ReflowReflow
    4. 31Post-flip-chip defluxCritical: flux in the gap
- UnderfillSteps 32–35
  1. 32BakeBake
  2. 33Plasma before underfillBetter flow & adhesion
  3. 34UnderfillUnderfill
  4. 35Underfill cureCure
Finishing
- ProtectionSteps 36–40
  1. 36MoldingMolding
  2. 37Post-mold cleanFlash & dust (molded)
  3. 38Pre-lid plasma cleanBy product
  4. 39Lid attachLid attach + TIM
  5. 40Laser markingMarking
- Ball mountSteps 41–44
  1. 41Plasma before ballsBy product
  2. Inline ball mount
    1. 42Flux · ball mountBall mount
    2. 43ReflowReflow
    3. 44Post-ball-mount deflux
- SingulationSteps 45–46
  1. Cleaned right after dicing
    1. 45SingulationUnit saw
    2. 46Post-dice cleanDust removal
Test and shipping
- TestSteps 47–50
  1. 47Final testFT
  2. 48Burn-in testBurn-in
  3. 49System-level testSLT, high-end chips
  4. 50Visual inspection
- Packing and shippingSteps 51–55
  1. 51Into traysJEDEC tray
  2. 52MSL bakeBy MSL
  3. One inline packer does it all
    1. 53Vacuum dry packBag + desiccant + HIC
    2. 54Label · inner box
  4. 55Carton · pallet
  5. ✓ Shipped

Wafer-level chip scale package (WLCSP)

Packaged on the whole wafer; each unit is die-sized. No substrate, so one line and no merge. All cleaning at wafer level.

32 process steps

Typical nodes: mostly mature 28 nm and above | small dies for power management, sensors, RF

NewsMany tiny power, sensor and RF chips in phones are WLCSP — the package is the chip.

WLCSP32 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Packaging flow

Wafer line
- Wafer intakeSteps 1–2
  1. 1Wafer intakeShipped from the fab
  2. 2Incoming inspectionIncoming QC
- RedistributionSteps 3–15
  1. 3Passivation 1PI/PBO litho & cure
  2. 4Passivation descumDescum
  3. 5Seed layer sputterSeed sputter
  4. 6Litho
  5. 7Pre-RDL treat
  6. 8RDL platingRDL Cu plating
  7. 9Post-RDL-plating rinse
  8. 10Strip · seed etchWet process
  9. 11Post-strip clean
  10. 12Passivation 2PI
  11. 13Passivation descumDescum
  12. 14Pre-UBM plasma clean
  13. 15UBMUBM
- Ball mountSteps 16–18
  1. Inline ball mount (wafer)
    1. 16Flux print · ball dropBall drop
    2. 17ReflowReflow
    3. 18Wafer-level defluxFlux around balls
- Grind & diceSteps 19–26
  1. 19Wafer probeCP
  2. Grinder cleans inline
    1. 20BackgrindingBack grinding
    2. 21Post-grind cleanRemoves debris
  3. 22Backside filmBackside laminate
  4. 23Laser markingMarking
  5. Saw cleans inline
    1. 24Wafer dicingWafer saw
    2. 25Post-dice clean
  6. 26Visual inspectionAOI
- Pick-and-testSteps 27–28
  1. 27Pick to reelPick & place
  2. 28Final testBy product
- Packing and shippingSteps 29–32
  1. 29MSL bakeBy MSL
  2. One inline packer does it all
    1. 30Vacuum dry packBag + desiccant + HIC
    2. 31Label · inner box
  3. 32Carton · pallet
  4. ✓ Shipped

Fan-out packaging (Fan-out / InFO)

Dies placed on a carrier and molded, then RDL fans connections out beyond the die. Chip-first shown; TSMC InFO is this type.

46 process steps

Typical nodes: advanced 16 nm and below | phone processors (the first volume product was Apple's 16 nm A10)

NewsTSMC first used InFO for the iPhone 7's A10 in 2016 (Semiconductor Digest) — thinner and cooler; later iPhones kept it.

Fan-out46 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Materials: 2 lines in parallel, merging at assembly

Wafer lineFrom the fab

Wafer intakeSteps 1–3
1. 1Wafer intakeShipped from the fab
2. 2Incoming inspectionIncoming QC
3. 3Wafer probeCP, at the fab or OSAT
Copper pillar growthSteps 4–5
1. 4Wafer copper postsCu post
2. 5Cu post cleansPre-treat · rinse · strip
Grind & diceSteps 6–12
1. 6Apply protective tapeBG tape
2. Grinder cleans inline
  1. 7BackgrindingBack grinding
  2. 8Post-grind cleanRemoves debris
3. 9Detape · tape mountWafer mount
4. Saw cleans inline
  1. 10Wafer dicingWafer saw
  2. 11Post-dice cleanDI spray + spin dry
5. 12Post-dicing inspectionAOI
Wafer to lineSteps 13–15
1. 13Load frame cassetteFrame cassette
2. 14N₂ cabinetBy product
3. 15To assemblyCart, AGV, or OHT

Carrier linePrepared in-house

Carrier preparationSteps 16–19
1. 16Carrier release coatCarrier + release
2. 17Backside RDLBackside RDL, for PoP
3. 18Through-mold viasTIV / TMV, for PoP
4. 19Post-TMV-plating cleanFor PoP
Carrier to lineStep 20
1. 20To assembly

Dies onto carrier

Main flow

Place & mold
- Place & moldSteps 21–25
  1. 21Kitting · lot matchingMatch lots, count
  2. 22Die placementFace-up + DAF
  3. 23Compression moldingCompression molding
  4. 24Mold grindingExpose Cu posts
  5. 25Post-grind cleanRemoves residue
RDL & balls
- RedistributionSteps 26–29
  1. 26Multilayer RDLRepeat several layers
  2. 27RDL descum (repeated)After each develop
  3. 28Per-layer RDL cleanPlating and strip
  4. 29UBMUBM
- Ball mountSteps 30–32
  1. Inline ball mount (wafer)
    1. 30Flux · ball mountBall mount
    2. 31ReflowReflow
    3. 32Wafer-level deflux
Debond & singulate
- Debond and singulationSteps 33–38
  1. 33Carrier debondCarrier debond
  2. 34Post-debond cleanRemoves adhesive
  3. 35Backside open · stackFor PoP
  4. 36Laser markingMarking
  5. Saw cleans inline
    1. 37SingulationSaw
    2. 38Post-dice clean
Test and shipping
- TestSteps 39–41
  1. 39Final testFT
  2. 40Burn-in testHigh-reliability
  3. 41Visual inspectionVisual / AOI
- Packing and shippingSteps 42–46
  1. 42Into traysJEDEC tray
  2. 43MSL bakeBy MSL
  3. One inline packer does it all
    1. 44Vacuum dry packBag + desiccant + HIC
    2. 45Label · inner box
  4. 46Carton · pallet
  5. ✓ Shipped

CoWoS (2.5D advanced packaging)

Three inputs: interposer wafers and compute chips (from fabs) and HBM (from memory makers). They merge on the interposer (CoW), then the module meets the substrate (oS). Two flip-chip bonds plus balls: at least three defluxes. CoWoS-S shown, from public sources.

73 process steps

Typical nodes: mainly 7 nm and below | AI accelerators: NVIDIA H100 (4 nm class), B200, B300 (4NP); first volume production was a 28 nm FPGA in 2013

In the newsAI accelerators from the NVIDIA H100 and B200 (TechInsights) to the latest B300 (Blackwell Ultra, CoWoS-L, HBM3E in 12-high stacks for 288 GB; TrendForce) all use CoWoS to package the GPU and HBM memory together. With AI demand surging, CoWoS capacity has become the bottleneck for AI chip shipments (AI Weekly).

CoWoS73 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Materials: 4 lines in parallel, merging at assembly

Interposer lineMade in the fab

InterposerSteps 1–6
1. 1Through-silicon viasTSV etch · fill · CMP
2. 2Post-CMP clean
3. 3Front-side RDLInterposer RDL
4. 4RDL descum (repeated)Descum
5. 5Per-layer RDL cleanPlating and strip
6. 6Micro-bump padsMicro-bump pad
Interposer to lineSteps 7–8
1. 7Load into FOUPFOUP
2. 8To assemblyOHT or AGV

Compute chipsFrom the fab

Micro-bumpsSteps 9–11
1. 9SoC wafer micro-bumpsMicro-bump
2. 10Micro-bump cleansPre-treat · rinse · strip
3. 11Wafer probeCP, pick KGD
Grind & diceSteps 12–15
1. Grinder cleans inline
  1. 12Grinding
  2. 13Post-grind cleanRemoves debris
2. Saw cleans inline
  1. 14Dicing
  2. 15Post-dice clean
Wafer to lineSteps 16–18
1. 16Load frame cassetteFrame cassette
2. 17N₂ cabinetBy product
3. 18To assemblyCart, AGV, or OHT

HBM lineFrom memory makers

HBMStep 19
1. 19HBM stack intakePre-stacked memory
HBM to lineSteps 20–21
1. 20Unpack · dry cabinet
2. 21To assembly

Substrate lineJoins at the 2nd merge

Substrate intakeStep 22
1. 22Substrate in · bake
Substrate to lineSteps 23–25
1. 23Load magazineMagazine
2. 24Dry cabinet storageBy product
3. 25To assembly

Merge 1: chips and HBM onto interposer

Main flow

CoW
- CoW bondingSteps 26–29
  1. 26Kitting · lot matchingMatch lots, count
  2. CoW bonding: inline with reflow
    1. 27Flux applicationFlux
    2. 28Chip bondingReflow or TCB
    3. 29CoW defluxHardest: <25 µm bumps
- Underfill and moldingSteps 30–36
  1. 30Bake
  2. 31Plasma before underfill
  3. 32UnderfillUnderfill
  4. 33Underfill cureCure
  5. 34Wafer-level moldingWafer molding
  6. 35Mold grinding
  7. 36Post-grind clean
Interposer back
- Backside and dicingSteps 37–48
  1. 37Temporary carrier bondTemporary bond
  2. 38Backgrind · TSV revealTSV reveal
  3. 39Post-reveal clean
  4. 40Backside passivation · RDL
  5. 41Backside RDL cleanPlating and strip
  6. 42C4 bumpsPlating + reflow
  7. 43Post-bump cleanBy process
  8. 44Carrier debondDebond
  9. 45Post-debond cleanRemoves adhesive
  10. Saw cleans inline
    1. 46CoW dicingWafer saw
    2. 47Post-dice clean
  11. 48CoW test
- To oS lineSteps 49–50
  1. 49Load trays
  2. 50To assembly

Merge 2: CoW onto substrate

After the merge

oS
- oS bondingSteps 51–55
  1. 51Kitting · lot matchingMatch lots, count
  2. Inline flip chip: conveyor to cleaner
    1. 52Flux applicationFlux
    2. 53Flip-chip bondingCoW on substrate
    3. 54ReflowReflow
    4. 55oS defluxLarge size, narrow gap
- Underfill and lidSteps 56–61
  1. 56Bake
  2. 57Plasma before underfill
  3. 58UnderfillUnderfill
  4. 59Underfill cureCure
  5. 60Pre-lid plasma cleanBy product
  6. 61Lid · stiffenerLid / stiffener + TIM
Balls & test
- Ball mountSteps 62–65
  1. 62Plasma before ballsBy product
  2. Inline ball mount
    1. 63Flux · ball mountBall mount
    2. 64ReflowReflow
    3. 65Post-ball-mount deflux
- TestSteps 66–68
  1. 66Final testFT
  2. 67System-level testSLT
  3. 68Visual inspection
- Packing and shippingSteps 69–73
  1. 69Into traysJEDEC tray
  2. 70MSL bakeBy MSL
  3. One inline packer does it all
    1. 71Vacuum dry packBag + desiccant + HIC
    2. 72Label · inner box
  4. 73Carton · pallet
  5. ✓ Shipped

CoPoS (panel 2.5D, in development)

Swaps CoWoS's round interposer for a 310×310 mm panel — reportedly a square CoWoS-L/R. Same merges as CoWoS. Not yet in production; expected flow from public info. More: What is CoPoS.

58 process steps

Typical nodes: expected to be the most advanced, 3 nm and below | large AI / HPC chips (after 2028)

NewsTSMC's CoPoS pilot line is at VisEra Longtan in 2026, with volume at AP7 Chiayi after 2H 2028 (Economic Daily News, T Kebang). See What is CoPoS.

CoPoS58 steps

Steps run top to bottom along blue arrows; parallel material lines merge below. Click for details.

Materials: 4 lines in parallel, merging at assembly

Panel lineOn a panel line

Panel interposerSteps 1–7
1. 1Panel carrier310×310 mm carrier
2. 2Release layer coatRelease layer
3. 3Multilayer RDLPanel RDL
4. 4RDL descum (repeated)Descum
5. 5Per-layer RDL cleanPlating and strip
6. 6Silicon bridgesLSI, CoWoS-L style
7. 7Micro-bump pads
Interposer to lineSteps 8–9
1. 8Load into FOUPFOUP
2. 9To assemblyOHT or AGV

Compute chipsFrom the fab

Micro-bumpsSteps 10–11
1. 10SoC bumps · probeKGD
2. 11Micro-bump cleansPre-treat · rinse · strip
Grind & diceSteps 12–15
1. Grinder cleans inline
  1. 12Grinding
  2. 13Post-grind cleanRemoves debris
2. Saw cleans inline
  1. 14Dicing
  2. 15Post-dice clean
Wafer to lineSteps 16–18
1. 16Load frame cassetteFrame cassette
2. 17N₂ cabinetBy product
3. 18To assemblyCart, AGV, or OHT

HBM lineFrom memory makers

HBMStep 19
1. 19HBM stack intake
HBM to lineSteps 20–21
1. 20Unpack · dry cabinet
2. 21To assembly

Substrate lineJoins at the 2nd merge

Substrate intakeStep 22
1. 22Substrate in · bake
Substrate to lineSteps 23–25
1. 23Load magazineMagazine
2. 24Dry cabinet storageBy product
3. 25To assembly

First merge: compute chips and HBM onto the panel

Main flow

CoP
- CoP bondingSteps 26–29
  1. 26Kitting · lot matchingMatch lots, count
  2. CoP bonding: panels suit conveyors
    1. 27Flux applicationFlux
    2. 28Chip bondingChip on panel
    3. 29Panel-level defluxEven across 310 mm
- Underfill and moldingSteps 30–36
  1. 30BakeFull-panel drying
  2. 31Plasma before underfill
  3. 32UnderfillUnderfill
  4. 33Underfill cure
  5. 34Panel moldingPanel molding
  6. 35Mold grinding
  7. 36Post-grind clean
Panel back & dicing
- Backside and dicingSteps 37–42
  1. 37Carrier debondDebond
  2. 38Post-debond cleanRemoves adhesive
  3. 39C4 bumps
  4. 40Post-bump cleanBy process
  5. Saw cleans inline
    1. 41Panel dicingPanel saw
    2. 42Post-dice clean
- To oS lineSteps 43–44
  1. 43Load trays
  2. 44To assembly

Merge 2: CoP onto substrate

After the merge

oS and back end
- oS bondingSteps 45–49
  1. 45Kitting · lot matchingMatch lots, count
  2. Inline flip chip
    1. 46Flip-chip to substrateSame as CoWoS
    2. 47oS Deflux
  3. 48Plasma before underfill
  4. 49Underfill · lid
- Ball mountSteps 50–52
  1. 50Plasma before ballsBy product
  2. Inline ball mount
    1. 51Ball mount · reflow
    2. 52Post-ball-mount deflux
- TestStep 53
  1. 53Final test · SLT
- Packing and shippingSteps 54–58
  1. 54Into traysJEDEC tray
  2. 55MSL bakeBy MSL
  3. One inline packer does it all
    1. 56Vacuum dry packBag + desiccant + HIC
    2. 57Label · inner box
  4. 58Carton · pallet
  5. ✓ Shipped

Shared stages

Wafer preparation
Incoming wafer inspection and wafer probe (CP) screen out bad dies; then the wafer is taped, backgrinded to the required thickness, and diced into dies. Wire-bond, flip-chip, and 2.5D packages all include this stage; wafer-level packages finish packaging on the whole wafer first and grind and dice last.
Assembly
This is where package types mainly differ: wire bonding after die attach, flip-chip reflow, die placement on a carrier followed by RDL, or bonding to an interposer first and then to a substrate. Any bonding step that uses flux must be followed by deflux.
Protection & contacts
Molding, underfill, and lids protect the die; leadframe packages need plating and trim-and-form to make leads, and BGA types need solder balls.
Test and shipping
Final test (FT) screens good units; high-reliability products add burn-in, and high-end processors add system-level test (SLT), followed by visual inspection and vacuum packing for shipment. For the packing stage, see the automatic semiconductor inner-box packing machine.

Two cases outside the 8 types

Hybrid bonding

E.g. TSMC SoIC and new HBM: copper-to-copper, no bumps or flux, so no deflux — but surfaces must be even cleaner.

FOPLP (panel-level fan-out)

Like fan-out, but on a square panel for more units per run. vs. CoPoS: CoPoS vs. FOPLP.

FAQ

Is a packaging plant one continuous line?

No. Wafers, substrates, memory, and other materials come from different factories, are prepared separately, and only merge at the bonding step. Each stage uses different carriers (wafers, substrate strips, single units) at different speeds, and there are batch processes such as baking and testing. So an OSAT is a series of standalone tools, with material moved in lots; only short, fixed sequences such as "flux → bond → reflow → deflux" are linked by conveyor.

What is the semiconductor packaging process flow?

There are roughly four stages: wafer preparation (intake, probe, grinding, dicing), assembly (wire bond, flip chip, or wafer-level RDL), protection and contacts (molding, underfill, lid, plating, or ball mount), and test and shipping. Packages differ most in the assembly stage, with step counts ranging from thirty-something to seventy-something.

What's the difference between QFN and BGA?

Both can be wire-bond packages. QFN uses a leadframe with metal pads around the bottom edge as contacts, molded as a strip and then singulated; BGA uses a substrate with a full array of solder balls on the bottom, giving many more contacts. BGA needs ball mounting, so it has an extra deflux step; QFN doesn't.

What's the difference between FCBGA and wire-bond BGA?

In wire-bond BGA, the die faces up and connects to the substrate with metal wires. In FCBGA, the die is flipped and soldered directly to the substrate with bumps, then underfilled. Flip chip gives shorter connections, more contacts, and better heat dissipation, so it's used for high-performance chips like CPUs and GPUs, but it adds bumping, post-flip-chip deflux, and underfill.

What's the difference between CoWoS and InFO?

Both are TSMC advanced packages. InFO is fan-out: dies are placed on a carrier, molded, and RDL is built directly on them with no separate substrate; it's mostly used for phone processors. CoWoS is 2.5D: multiple chips connect to an interposer and then to a substrate; it's used for AI accelerators, with a longer process and more deflux steps.

Why does WLCSP have no substrate?

WLCSP builds the RDL and solder balls directly on the whole wafer, so each diced unit is die-sized and its solder balls go straight onto the circuit board. No leadframe or substrate is needed, which suits small chips in phones.

What packages do 3 nm and 5 nm chips use?

It depends on the product. AI accelerators mostly use 2.5D advanced packaging like CoWoS, CPUs and GPUs use FCBGA, and phone processors use fan-out InFO or flip-chip FCCSP. Advanced-node chips have many contacts and run hot, so wire-bond packaging is rarely used.

What packages do mature-node (28 nm and above) chips use?

Mostly wire-bond packages such as QFN, QFP, and wire-bond BGA, or very small WLCSP. Power management, analog, MCU, and sensor products have few contacts and are cost-sensitive, so wire bonding is the best value.

Which packaging steps require cleaning?

Every package has post-dicing cleaning. Bonding that uses flux (flip chip, ball mount) needs deflux afterward; molding may need deflash; plasma cleaning is common before wire bonding and underfill. For the number of cleaning stations per package, see the comparison table in this article.

Sag trips on your packaging line?

Reflow ovens, bonders and testers can trip in a sag and scrap a lot. The VSP guards controls in 1 ms. Cleaning or packing questions? Ask us too.

Back-end flowcharts: 8 package types compared

Summary: what are the steps in packaging?

What packaging does

Protection

Connection

Heat dissipation

Test

4 families by connection

The 8 packages compared

Which package for which node?

Full flows for 8 packages

Leadframe packages (QFP / SOP)

QFN / DFN (no-lead leadframe)

Wire-bond BGA (PBGA)

Flip-chip BGA (FCBGA / FCCSP)

Wafer-level chip scale package (WLCSP)

Fan-out packaging (Fan-out / InFO)

CoWoS (2.5D advanced packaging)

CoPoS (panel 2.5D, in development)

Shared stages

Wafer preparation

Assembly

Protection & contacts

Test and shipping

Two cases outside the 8 types

Hybrid bonding

FOPLP (panel-level fan-out)

FAQ

Further reading

Sag trips on your packaging line?

Can't find the answer? Ask us directly