Semiconductor process flowcharts: crystal growth to packaging

Silicon wafers: crystal growth to polished wafer

Where chips begin: 11-nines polysilicon is melted and pulled (CZ) into a 300 mm, 2 m ingot, then sliced, lapped and polished flat. SiC wafers grow by PVT at fractions of a mm per hour — why they're costly.

34 steps (repeats counted once)

NewsAI is lifting demand for 300 mm wafers; SiC is moving from 6- to 8-inch for EVs and chargers.

Advanced logic (3 / 2 nm class, GAA nanosheet transistors)

Compute chips for CPUs, GPUs, phones and AI. Shown with GAA nanosheets; FinFET is similar, minus the nanosheet steps. Dozens of masks, 10+ metal layers.

67 steps (repeats counted once)

NewsTSMC N3 powers the latest Apple and NVIDIA chips; N2 moves to GAA nanosheets, in volume since 2H 2025.

DRAM (1β nm class)

Main memory for PCs and phones, and the basis of HBM. Each cell is one transistor + one capacitor: buried word line, bit line above, tall capacitor on top. HBM wafers also get TSVs for stacking.

60 steps (repeats counted once)

NewsAI servers eat HBM, so memory makers shift DRAM capacity to it — and prices rise.

3D NAND flash (200+ layers)

Storage for SSDs and phones. Cells stacked 200+ layers high: deposit hundreds of films, then etch deep holes in one pass. Periphery often sits under the array (CuA) or on a bonded wafer.

54 steps (repeats counted once)

NewsAI data centers drive enterprise SSDs; layers push past 300.

Power devices (trench MOSFET / IGBT)

Power switches for EVs, chargers, inverters and motors. Trench MOSFET shown: current runs vertically, so the back gets metal too. IGBTs add a backside implant; SiC needs 1600 °C+ activation. Mostly 200/150 mm fabs.

41 steps (repeats counted once)

NewsEVs and AI power supplies drive SiC and GaN; Taiwan is adding 200 mm capacity.

Leadframe packages (QFP / SOP)

The classic package: die on a metal leadframe, wire bonded, leads on two or four sides. No solder balls, so no deflux.

39 process steps

Nodes: 90 nm+ | auto MCUs, power ICs, industrial

NewsCar engine and body electronics rely on QFP MCUs — the mature chips missing in the 2021 shortage.

QFN / DFN (no-lead leadframe)

Leads hidden underneath; the whole strip is molded, then cut (MAP). Wire bonded, no deflux; cleaning is dicing and deflash.

40 process steps

Typical nodes: mature 28 nm and above | power management, analog, RF, Bluetooth chips

NewsPower, charging and wireless chips in phones, earbuds and watches: small, cool, cheap.

Wire-bond BGA (PBGA)

Die face-up on a substrate, wire bonded, solder balls below. Balls need flux, so one deflux.

42 process steps

Nodes: 28 nm+ | consumer SoCs, networking, industrial

NewsDRAM and NAND often stack dies, wire bond them and package as BGA.

Flip-chip BGA (FCBGA / FCCSP)

Die flipped and bumped onto the substrate, then underfilled. Same data as the deflux article. FCCSP is the small version, often with molded underfill.

55 process steps

Typical nodes: 40 nm to 3 nm | CPUs, GPUs, network switch chips; high-end products mostly 7 nm and below

NewsCPUs, GPUs and switch chips are all flip chip — too many pins and too much power for wires.

Wafer-level chip scale package (WLCSP)

Packaged on the whole wafer; each unit is die-sized. No substrate, so one line and no merge. All cleaning at wafer level.

32 process steps

Typical nodes: mostly mature 28 nm and above | small dies for power management, sensors, RF

NewsMany tiny power, sensor and RF chips in phones are WLCSP — the package is the chip.

Fan-out packaging (Fan-out / InFO)

Dies placed on a carrier and molded, then RDL fans connections out beyond the die. Chip-first shown; TSMC InFO is this type.

46 process steps

Typical nodes: advanced 16 nm and below | phone processors (the first volume product was Apple's 16 nm A10)

NewsTSMC first used InFO for the iPhone 7's A10 in 2016 (Semiconductor Digest) — thinner and cooler; later iPhones kept it.

CoWoS (2.5D advanced packaging)

Three inputs: interposer wafers and compute chips (from fabs) and HBM (from memory makers). They merge on the interposer (CoW), then the module meets the substrate (oS). Two flip-chip bonds plus balls: at least three defluxes. CoWoS-S shown, from public sources.

73 process steps

Typical nodes: mainly 7 nm and below | AI accelerators: NVIDIA H100 (4 nm class), B200, B300 (4NP); first volume production was a 28 nm FPGA in 2013

In the newsAI accelerators from the NVIDIA H100 and B200 (TechInsights) to the latest B300 (Blackwell Ultra, CoWoS-L, HBM3E in 12-high stacks for 288 GB; TrendForce) all use CoWoS to package the GPU and HBM memory together. With AI demand surging, CoWoS capacity has become the bottleneck for AI chip shipments (AI Weekly).

CoPoS (panel 2.5D, in development)

Swaps CoWoS's round interposer for a 310×310 mm panel — reportedly a square CoWoS-L/R. Same merges as CoWoS. Not yet in production; expected flow from public info. More: What is CoPoS.

58 process steps

Typical nodes: expected to be the most advanced, 3 nm and below | large AI / HPC chips (after 2028)

NewsTSMC's CoPoS pilot line is at VisEra Longtan in 2026, with volume at AP7 Chiayi after 2H 2028 (Economic Daily News, T Kebang). See What is CoPoS.