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Front-end Process・Wafer Fabrication Flow Charts

Front-end flowcharts: logic, DRAM, 3D NAND, power

Front-end processing happens in the fab, turning a blank silicon wafer into a wafer full of circuits before it goes to an OSAT for the back end. Different products are made very differently: advanced logic pushes transistors to be as small as possible, DRAM needs tall, thin capacitors, 3D NAND stacks hundreds of layers, and power devices send large currents vertically through the wafer. This page charts the modules and steps for 4 products from wafer intake to shipment, 222 steps in all, with repeated steps marked by count. Together with the crystal growth flowchart (34 steps) and the back-end flowcharts (8 packages, 385 steps), you can follow more than 600 steps from crystal growth to shipment, each one explained.

By Lawrence Hsu, COO, DEYly
Published · Last updated

4 products

All 4 products use the same kind of silicon wafer (power devices also use SiC wafers), supplied by upstream wafer makers after crystal growth, slicing, and polishing. Once the fab receives them, each product follows its own flow.

Click a product name to switch to its flowchart
ProductTypical productsNode and waferKey traitsPackaging
Advanced logicCPUs, GPUs, phone processors, AI accelerators3 / 2 nm class; 300 mmSmallest transistors, most masks, 10+ metal layersFCBGA, fan-out InFO, CoWoS
DRAMComputer and phone memory, HBM1β nm class; 300 mm1 transistor + 1 tall capacitorWire-bond BGA; HBM stacks go into CoWoS
3D NANDSSDs, phones200–300+ layer stacks; 300 mmStack hundreds of films, etch deep holesWire-bond BGA (multi-die stacks)
Power devicesEVs, chargers, solar inverters, industrial motorsMicrons; 200/150 mmVertical current; backside metalQFP, QFN, power modules

Front-end flows

Inside the fab, processing is also divided into FEOL (transistors), MOL (contacts), and BEOL (metal interconnect). All three happen in the fab and differ from back-end packaging at an OSAT. This page is compiled from public textbooks and industry data; each fab's actual steps, layer counts, and recipes differ and are mostly confidential.

Advanced logic (3 / 2 nm class, GAA nanosheet transistors)

Compute chips for CPUs, GPUs, phones and AI. Shown with GAA nanosheets; FinFET is similar, minus the nanosheet steps. Dozens of masks, 10+ metal layers.

67 steps (repeats counted once)

NewsTSMC N3 powers the latest Apple and NVIDIA chips; N2 moves to GAA nanosheets, in volume since 2H 2025.

Advanced logic67 steps

One row per module; follow the blue arrows. Orange dashed boxes repeat (count shown). Click for details.

Teal ↗: related articleHalf blue, half teal ↗: both product and articleOrange dashed box: repeated steps (count marked)Blue arrow: continues to next stepGreen box: end of flow
Wafer preparation
  • Wafer preparationSteps 1–5
    1. 1Wafer intake300 mm wafers
    2. 2Incoming inspectionFlatness · defects
    3. 3Laser markingWafer ID
    4. 4Initial wet cleanRCA clean
    5. 5Load into FOUPFOUP from here on
Next: transistors (FEOL)
Transistors (FEOL)
  • Fins and isolationSteps 6–15
    1. 6Si/SiGe epi stackFor GAA nanosheets
    2. 7Hard mask deposition
    3. 8LithographyTrack + scanner
    4. 9CD · overlayCD-SEM / overlay
    5. 10Fin etchDry plasma etch
    6. 11Resist strip · cleanAshing + wet clean
    7. 12STI fillSTI: oxide deposition
    8. 13CMP planarization
    9. 14Post-CMP clean
    10. 15Fin revealOxide etch-back
  • Well implantSteps 16–19
    1. ↻ Repeat × several (wells, Vt)
      1. 16LithographyTrack + scanner
      2. 17Ion implantationN-well / P-well
      3. 18Resist strip · cleanAshing + wet clean
    2. 19Rapid thermal annealRTA: dopant activation
  • Dummy gate and spacersSteps 20–25
    1. 20Gate oxide · polyDummy gate
    2. 21LithographyTrack + scanner
    3. 22CD · overlayCD-SEM / overlay
    4. 23Gate etch
    5. 24Resist strip · cleanAshing + wet clean
    6. 25Spacer dep & etchSpacer
  • Source / drainSteps 26–30
    1. 26Source/drain recess
    2. 27Inner spacerIsolates nanosheets
    3. 28CleanPre-epi clean
    4. 29Source/drain epitaxyPMOS SiGe / NMOS SiP
    5. 30Laser anneal
  • Replacement metal gateSteps 31–37
    1. 31ILD deposition · CMPILD0
    2. 32Dummy gate removal
    3. 33Nanosheet releaseSelective SiGe etch
    4. 34Clean
    5. 35High-k gate dielectricALD: HfO₂
    6. 36Work-function metalALD: sets Vt
    7. 37Gate metal fill · CMP
Next: contacts (MOL)
Contacts (MOL)
  • ContactsSteps 38–46
    1. 38Dielectric deposition
    2. 39LithographyTrack + scanner
    3. 40CD · overlayCD-SEM / overlay
    4. 41Contact etch
    5. 42Resist strip · cleanAshing + wet clean
    6. 43Silicide formationLower resistance
    7. 44Contact metal fillTungsten or cobalt
    8. 45CMP planarization
    9. 46Post-CMP clean
Next: interconnect (BEOL)
Back-end interconnect (BEOL)
  • Metal interconnectSteps 47–56
    1. ↻ Repeat × 12–15 layers
      1. 47Low-k depositionLow-k
      2. 48EUV or multi-patterningEUV for finest layers
      3. 49CD · overlayCD-SEM / overlay
      4. 50Trench · via etchDual damascene
      5. 51Resist strip · cleanAshing + wet clean
      6. 52Barrier · Cu seedPVD
      7. 53Copper electroplating
      8. 54Copper CMP
      9. 55Post-CMP clean
      10. 56Defect inspection
  • Top metal & passivationSteps 57–61
    1. 57Thick metal · Al pads
    2. 58Passivation depositionSiN · SiO₂
    3. 59LithographyTrack + scanner
    4. 60Pad open etchPad open
    5. 61Resist strip · cleanAshing + wet clean
Next: test
Test
  • Wafer testSteps 62–63
    1. 62Wafer acceptance testWAT: scribe-line tests
    2. 63Wafer probeCP: per-die test
Next: shipping
Shipping
  • ShippingSteps 64–67
    1. 64Outgoing inspectionLook · defects · data
    2. 65Into FOSBFOSB
    3. 66Vacuum dry packBag + desiccant, sealed
    4. 67Ship to OSATContinues to back end
    5. ✓ Wafers to the OSAT

DRAM (1β nm class)

Main memory for PCs and phones, and the basis of HBM. Each cell is one transistor + one capacitor: buried word line, bit line above, tall capacitor on top. HBM wafers also get TSVs for stacking.

60 steps (repeats counted once)

NewsAI servers eat HBM, so memory makers shift DRAM capacity to it — and prices rise.

DRAM60 steps

One row per module; follow the blue arrows. Orange dashed boxes repeat (count shown). Click for details.

Teal ↗: related articleHalf blue, half teal ↗: both product and articleOrange dashed box: repeated steps (count marked)Blue arrow: continues to next stepGreen box: end of flow
Wafer preparation
  • Wafer preparationSteps 1–5
    1. 1Wafer intake300 mm wafers
    2. 2Incoming inspectionFlatness · defects
    3. 3Laser markingWafer ID
    4. 4Initial wet cleanRCA clean
    5. 5Load into FOUPFOUP from here on
Next: memory cell array
Memory cell array
  • Active area & isolationSteps 6–14
    1. 6Hard mask deposition
    2. ↻ Multi-patterning × 2–4
      1. 7LithographyTrack + scanner
      2. 8Etch · spacer transferSAQP patterning
    3. 9CD · overlayCD-SEM / overlay
    4. 10Active area etch
    5. 11Resist strip · cleanAshing + wet clean
    6. 12STI fillSTI
    7. 13CMP planarization
    8. 14Post-CMP clean
  • Buried word lineSteps 15–20
    1. 15LithographyTrack + scanner
    2. 16Word line trench etch
    3. 17Resist strip · cleanAshing + wet clean
    4. 18Gate oxidation
    5. 19Gate metal fillTiN / W
    6. 20Recess · cap
  • Bit lineSteps 21–28
    1. 21LithographyTrack + scanner
    2. 22Bit line contact etch
    3. 23Resist strip · cleanAshing + wet clean
    4. 24Bit line metal
    5. 25LithographyTrack + scanner
    6. 26Bit line etch
    7. 27Resist strip · cleanAshing + wet clean
    8. 28Spacer deposition
  • Storage capacitorSteps 29–37
    1. 29Storage node contactSNC
    2. 30Capacitor moldHigh aspect ratio
    3. 31LithographyTrack + scanner
    4. 32Capacitor hole etchAspect ratio above 50
    5. 33Resist strip · cleanAshing + wet clean
    6. 34Bottom electrodeTiN
    7. 35Mold removalWet etch
    8. 36Capacitor dielectricALD: high-k material
    9. 37Top electrode
Next: peripheral circuits
Periphery
  • Peripheral transistorsSteps 38–42
    1. ↻ Repeat × several (N, P)
      1. 38LithographyTrack + scanner
      2. 39Ion implantation
      3. 40Resist strip · cleanAshing + wet clean
    2. 41Peripheral gate
    3. 42Rapid thermal annealRTA
Next: metal interconnect
Metal
  • Metal interconnectSteps 43–49
    1. ↻ Repeat per layer × 3–4
      1. 43Dielectric deposition
      2. 44LithographyTrack + scanner
      3. 45Trench · via etch
      4. 46Resist strip · cleanAshing + wet clean
      5. 47Metal depositionW / Cu / Al
      6. 48CMP planarization
      7. 49Post-CMP clean
  • PassivationSteps 50–53
    1. 50Passivation deposition
    2. 51LithographyTrack + scanner
    3. 52Pad open etch
    4. 53Resist strip · cleanAshing + wet clean
Next: test
Test
  • Wafer testSteps 54–56
    1. 54Wafer acceptance testWAT: scribe-line tests
    2. 55Laser repairSwap in spare cells
    3. 56Wafer probeCP: per-die test
Next: shipping
Shipping
  • ShippingSteps 57–60
    1. 57Outgoing inspectionLook · defects · data
    2. 58Into FOSBFOSB
    3. 59Vacuum dry packBag + desiccant, sealed
    4. 60Ship to OSATContinues to back end
    5. ✓ Wafers to the OSAT

3D NAND flash (200+ layers)

Storage for SSDs and phones. Cells stacked 200+ layers high: deposit hundreds of films, then etch deep holes in one pass. Periphery often sits under the array (CuA) or on a bonded wafer.

54 steps (repeats counted once)

NewsAI data centers drive enterprise SSDs; layers push past 300.

3D NAND54 steps

One row per module; follow the blue arrows. Orange dashed boxes repeat (count shown). Click for details.

Teal ↗: related articleHalf blue, half teal ↗: both product and articleOrange dashed box: repeated steps (count marked)Blue arrow: continues to next stepGreen box: end of flow
Wafer preparation
  • Wafer preparationSteps 1–5
    1. 1Wafer intake300 mm wafers
    2. 2Incoming inspectionFlatness · defects
    3. 3Laser markingWafer ID
    4. 4Initial wet cleanRCA clean
    5. 5Load into FOUPFOUP from here on
Next: periphery (under array)
Periphery (under array)
  • Peripheral transistorsSteps 6–13
    1. ↻ Repeat × several
      1. 6LithographyTrack + scanner
      2. 7Ion implantation
      3. 8Resist strip · cleanAshing + wet clean
    2. 9Peripheral gate
    3. 10Rapid thermal annealRTA
    4. 11Lower metal
    5. 12CMP planarization
    6. 13Post-CMP clean
Next: memory array stack
Array stack
  • Multilayer film stackSteps 14–15
    1. ↻ Alternate × 200–300 layers
      1. 14SiO₂ deposition
      2. 15SiN deposition
  • Channel holesSteps 16–24
    1. ↻ Stacked in 2–3 decks
      1. 16Hard mask deposition
      2. 17LithographyTrack + scanner
      3. 18CD · overlayCD-SEM / overlay
      4. 19Channel hole etchAspect ratio above 60
      5. 20Resist strip · cleanAshing + wet clean
    2. 21Charge-trap layerONO
    3. 22Channel poly
    4. 23Hole fill · CMP
    5. 24Post-CMP clean
  • StaircaseSteps 25–29
    1. ↻ Trim + etch × dozens
      1. 25LithographyTrack + scanner
      2. 26Staircase etch
      3. 27Resist trim
    2. 28Resist strip · cleanAshing + wet clean
    3. 29Dielectric fill · CMP
  • Gate replacementSteps 30–35
    1. 30LithographyTrack + scanner
    2. 31Slit etch
    3. 32Resist strip · cleanAshing + wet clean
    4. 33SiN removalHot phosphoric etch
    5. 34Tungsten word lines
    6. 35Slit fill
Next: contacts & metal
Contacts & metal
  • Contacts & metalSteps 36–48
    1. 36LithographyTrack + scanner
    2. 37Staircase contact etchVarying depths
    3. 38Resist strip · cleanAshing + wet clean
    4. 39Contact metal fill
    5. ↻ Repeat per layer × 2–3
      1. 40Dielectric deposition
      2. 41LithographyTrack + scanner
      3. 42Trench · via etch
      4. 43Resist strip · cleanAshing + wet clean
      5. 44Metal deposition
      6. 45CMP planarization
      7. 46Post-CMP clean
    6. 47Passivation deposition
    7. 48Pad open etch
Next: test
Test
  • Wafer testSteps 49–50
    1. 49Wafer acceptance testWAT: scribe-line tests
    2. 50Wafer probeCP: per-die test
Next: shipping
Shipping
  • ShippingSteps 51–54
    1. 51Outgoing inspectionLook · defects · data
    2. 52Into FOSBFOSB
    3. 53Vacuum dry packBag + desiccant, sealed
    4. 54Ship to OSATContinues to back end
    5. ✓ Wafers to the OSAT

Power devices (trench MOSFET / IGBT)

Power switches for EVs, chargers, inverters and motors. Trench MOSFET shown: current runs vertically, so the back gets metal too. IGBTs add a backside implant; SiC needs 1600 °C+ activation. Mostly 200/150 mm fabs.

41 steps (repeats counted once)

NewsEVs and AI power supplies drive SiC and GaN; Taiwan is adding 200 mm capacity.

Power devices41 steps

One row per module; follow the blue arrows. Click a box for details.

Blue ↗: related DEYly productTeal ↗: related articleHalf blue, half teal ↗: both product and articleDashed box: depends on productBlue arrow: continues to next stepGreen box: end of flow
Wafer preparation
  • Wafer preparationSteps 1–5
    1. 1Epi wafer intakeN⁺ substrate + N⁻ epi
    2. 2Incoming inspection
    3. 3Laser markingWafer ID
    4. 4Initial wet cleanRCA clean
    5. 5Load wafer cassette200 / 150 mm cassette
Next: front-side devices
Front side
  • Trench gateSteps 6–12
    1. 6Hard mask deposition
    2. 7LithographyTrack + scanner
    3. 8Trench etch
    4. 9Resist strip · cleanAshing + wet clean
    5. 10Sacrificial oxideRepairs trench surface
    6. 11Gate oxidationFurnace
    7. 12Poly fill · etch-back
  • Body and sourceSteps 13–20
    1. 13LithographyTrack + scanner
    2. 14Body implantP-type
    3. 15Resist strip · cleanAshing + wet clean
    4. 16Drive-inFurnace
    5. 17LithographyTrack + scanner
    6. 18Source implantN⁺
    7. 19Resist strip · cleanAshing + wet clean
    8. 20Activation anneal
  • Front-side metalSteps 21–30
    1. 21ILD deposition
    2. 22LithographyTrack + scanner
    3. 23Contact etch
    4. 24Resist strip · cleanAshing + wet clean
    5. 25Barrier layerTi / TiN
    6. 26Thick Al depositionSeveral µm
    7. 27LithographyTrack + scanner
    8. 28Metal etch
    9. 29Resist strip · cleanAshing + wet clean
    10. 30Passivation layerPolyimide
Next: backside processing
Backside
  • BacksideSteps 31–35
    1. 31Temp bond · thinningBackgrinding
    2. 32Post-grind clean
    3. 33Backside implantIGBT collector only
    4. 34Backside laser annealIGBT
    5. 35Backside metalTi / Ni / Ag
Next: test
Test
  • Wafer testSteps 36–37
    1. 36Wafer acceptance testWAT: scribe-line tests
    2. 37Wafer probeCP: per-die test
Next: shipping
Shipping
  • ShippingSteps 38–41
    1. 38Outgoing inspectionLook · defects · data
    2. 39Into FOSBFOSB
    3. 40Vacuum dry packBag + desiccant, sealed
    4. 41Ship to OSATContinues to back end
    5. ✓ Wafers to the OSAT

Sag trips on fab tools?

A tripped scanner, etcher or implanter can scrap 25 wafers and take hours to requalify. The VSP guards controls, switching in 1 ms. See SEMI F47.

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